Speedup of Self-Timed Digital Systems Using Early Completion

An Early Completion technique is developed to significantly increase the throughput of NULL Convention self-timed digital systems without impacting latency or compromising their self-timed nature. Early Completion performs the completion detection for registration stagei at the input of the register, instead of at the output of the register, as in standard NULL Convention Logic. This method requires that the singlerail completion signal from registration stagei+1, Koi+1, be used as an additional input to the completion detection circuitry for registration stagei, to maintain self-timed operation. However, Early Completion does necessitate an assumption of equipotential regions, introducing a few easily satisfiable timing assumptions, thus making the design potentially more delay-sensitive. To illustrate the technique, Early Completion is applied to a case study of the optimally pipelined 4-bit by 4-bit unsigned multiplier utilizing full-word completion, presented in [1], where a speedup of 1.21 is achieved while self-timed operation is maintained and latency remains unchanged.